DSP56F805PB/d rev. 4.0 , 1/2002 ? motorola, inc., 2002. all rights reserved. dsp56f805 product brief dsp56f805 16-bit digital signal processor ? up to 40 mips at 80 mhz core frequency ? dsp and mcu functionality in a unified, c-efficient architecture ? hardware do and rep loops ? mcu-friendly instruction set supports both dsp and controller functions: mac, bit manipulation unit, 14 addressing modes ?31.5k 16-bit words program flash ? 512 16-bit words program ram ?4k 16-bit words data flash ?2k 16-bit words data ram ?2k 16-bit words bootflash ? up to 64k 16-bit words each of external program and data memory ? two 6-channel pwm modules ? two 4-channel, 12-bit adcs ? two quadrature decoders ? can 2.0 b module ? two serial communication interfaces (scis) ? serial peripheral interface (spi) ? up to four general purpose quad timers ?jtag/once tm port for debugging ? 14 dedicated and 18 shared gpio lines ? 144-pin lqfp package figure 1. dsp56f805 block diagram jtag/ once port digital reg analog reg low voltage supervisor program controller and hardware looping unit data alu 16 x 16 + 36 ? 36-bit mac three 16-bit input registers two 36-bit accumulators address generation unit bit manipulation unit pll clock gen 16-bit dsp56800 core pa b pdb xdb2 cgdb xab1 xab2 xtal extal interrupt controls ipbb controls ipbus bridge (ipbb) module controls address bus [8:0] data bus [15:0] cop reset reset irqa irqb application- specific memory & peripherals interrupt controller program memory 32252 x 16 flash 512 x 16 sram boot flash 2048 x 16 flash data memory 4096 x 16 flash 2048 x 16 sram cop/ watchdog spi or gpio sci0 or gpio quad timer d / alt func quad timer c a/d1 a/d2 adc 4 2 4 4 4 4 6 pwm outputs fault inputs pwma 16 16 vcapc v dd v ss v dda v ssa 6 28 8* extboot current sense inputs 3 quadrature decoder 0/ quad timer a can 2.0a/b 2 clko external address bus switch bus control external data bus switch external bus interface unit rd enable wr enable ds select ps select 10 16 6 a[00:05] d[00:15] a[06:15] or gpio-e2:e3 & gpio-a0:a7 4 4 6 pwm outputs fault inputs pwmb current sense inputs 3 quadrature decoder 1/ quad b timer 4 2 sci1 or gpio 2 dedicated gpio 14 vpp rsto vref * includes tcs pin which is reserved for factory use and is tied to vss
2 dsp56f805 product brief motorola dsp56800 digital signal processing core features ? efficient 16-bit dsp56800 family dsp engine with dual harvard architecture ? as many as 40 million instructions per second (mips) at 80 mhz core frequency ? single-cycle 16 16-bit parallel multiplier-accumulator (mac) ? two 36-bit accumulators, including extension bits ? 16-bit bidirectional barrel shifter ? parallel instruction set with unique dsp addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? controller style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ? jtag/once debug programming interface dsp56f805 memory features ? harvard architecture permits as many as three simultaneous accesses to program and data memory ? on-chip memory including a low cost, high volume flash solution 31.5k 16 bit words of program flash 512 16-bit words of program ram 4k 16-bit words of data flash 2k 16-bit words of data ram 2k 16-bit words of bootflash ? off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states as much as 64k 16 bits of data memory as much as 64k 16 bits of program memory dsp56f805 peripheral circuit features ? two pulse width modulator modules each with six pwm outputs, three current sense inputs, and four fault inputs, fault tolerant design with dead-time insertion; supports both center- and edge- aligned modes ? 12-bit analog-to-digital converters (adc) which support two simultaneous conversions; adc and pwm modules can be run in sync ? two quadrature decoders each with four inputs or two additional quad timers ? two general purpose quad timers totaling six pins: timer c with two pins and timer d with four pins ? two serial communication interfaces, each with two pins (or four additional gpio lines) ? can 2.0 b module with 2-pin port for transmit and receive
motorola dsp56f805 product brief 3 ? serial peripheral interface (spi) with configurable four-pin port (or four additional gpio lines) ? 14 dedicated general purpose i/o (gpio) pins, 18 multiplexed gpio pins ? computer operating properly (cop) watchdog timer ? two dedicated external interrupt pins ? external reset input pin for hardware reset ? external reset output pin for system reset ? jtag/on-chip emulation (once?) module for unobtrusive, processor speed-independent debugging ? software-programmable, phase lock loop-based frequency synthesizer for the dsp core clock energy information ? fabricated in high-density cmos with 5v tolerant, ttl-compatible digital inputs ? uses a single 3.3v power supply ? on-chip regulators for digital and analog circuitry to lower cost and reduce noise ? wait and stop modes available dsp56f805 description the dsp56f805 is a member of the dsp56800 core-based family of digital signal processors (dsps). it combines, on a single chip, the processing power of a dsp and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. because of its low cost, configuration flexibility, and compact program code, the dsp56f805 is well-suited for many applications. the dsp56f805 includes many peripherals that are especially useful for applications such as: motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, and industrial control for power, lighting, automation. the dsp56800 core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers to enable rapid development of optimized control applications. best in class development environment the sdk (software development kit) provides fully debugged peripheral drivers, libraries and interfaces that allow programmers to create their unique c application code independent of component architecture. the codewarrior integrated development environment is a sophisticated tool for code navigation, compiling, and debugging. a complete set of evaluation modules (evms) and development system cards will support concurrent engineering. together, the sdk, codewarrior, and evms create a complete, scalable tools solution for easy, fast, and efficient development. product documentation the four documents listed in table 1 are required for a complete description and proper design with the dsp56f805. documentation is available from local motorola distributors, motorola semiconductor sales offices, motorola literature distribution centers, or online at www.motorola.com/semiconductors/dsp.
DSP56F805PB/d motorola and the stylized m logo are registered in the us patent & trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002. how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 5405, denver, colorado 80217. 1C303C675C2140 or 1C800C441C2447 japan: motorola japan ltd.; sps, technical information center, 3C20C1, minamiCazabu. minatoCku, tokyo 106C8573 japan. 81C3C3440C3569 asia/pacific: motorola semiconductors h.k. ltd.; silicon harbour centre, 2 dai king street, tai po industrial estate, tai po, n.t., hong kon g . 852C26668334 technical information center: 1C800C521C6274 home page: http://www.motorola.com/semiconductors/ motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application o r use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical param eters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all oper ating parameters, including typicals must be validated for each customer application by customers technical experts. motorola does not convey any licens e under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for sur gical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product cou ld create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer s hall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expens es, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. table 1. dsp56f805 chip documentation ordering information consult a motorola semiconductor sales office or authorized distributor to order parts. topic description order number dsp56800 family manual detailed description of the dsp56800 family architecture, and 16-bit dsp core processor and the instruction set dsp56800fm/d dsp56f801/803/805/807 users manual detailed description of memory, peripherals, and interfaces of the dsp56f805, dsp56f803, dsp56f805, and dsp56f807 dsp56f801-07um/d dsp56f805 technical data sheet electrical and timing specifications, pin descriptions, and package descriptions dsp56f805/d dsp56f805 product brief summary description and block diagram of the dsp56f805 core, memory, peripherals and interfaces (this document) DSP56F805PB/d table 2. dsp56f805 ordering information part supply voltage package type pin count frequency (mhz) order number dsp56f805 3.0C3.6 v plastic quad flat pack (lqfp) 144 80 dsp56f805fv80
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